The present invention relates to a clock recovery circuit, and more particularly, to a clock recovery circuit for extracting multiphase clocks synchronizing with data from the data.
For transmission/reception of data, a clock is necessary together with the data. The clock is a signal serving as a reference of timing for retrieval of the data. In data communications over some distance, such as data communications between mutually connected equipment units, if a data path and a clock path are provided separately, the phase relationship between the data and the clock set on the transmitter side may not be precisely received on the receiver side in some cases, due to a difference in path length and a difference in distortion level. As a result, high-speed data communications may not be attained. To solve this problem, a clock recovery technology is adopted in which a clock is extracted from transitions of data on the receiver side and recovered.
FIG. 17A shows a configuration of a conventional clock recovery circuit disclosed in Japanese Laid-Open Patent Publication No. 8-213979. The clock recovery circuit of FIG. 17A includes VCOs 100 and 101, a delay circuit 102 and logic circuits 103 and 104. The VCO 100 oscillates at a frequency corresponding to a bias voltage BIAS. The VCO 101 is identical in configuration to the VCO 100. The delay circuit 102 delays an asynchronous input data signal Data by a half period of the transmission rate. The logic circuit 103 computes exclusive OR of the input data signal Data and a signal from the delay circuit 102. In other words, the logic circuit 103 outputs low pulses having a width of a half period of the transmission rate of the input data signal Data. The logic circuit 104 computes AND of a signal output from the VCO 101 and a signal output from the logical circuit 103.
As shown in FIG. 17B, in the clock recovery circuit described above, the logic circuit 103 outputs a signal Gdat, which is put in an L level for a duration of a half of the transmission rate of the input data signal Data in response to a transition of the input data signal Data. The logic circuit 104 computes AND of a clock generated by the VCO 101 and the signal Gdat from the logic circuit 103, to thereby extract a clock ECK synchronizing with the asynchronous input data signal Data. With the configuration described above, the clock phase can be instantaneously locked with the input data as long as the VCO 101 has been locked at a predetermined frequency.
However, because the clock recovery circuit of FIG. 17A uses the single-phase clock ECK, the oscillating frequency of the VCO 101 must be equal to the data rate of the input data signal Data. In addition, because the logic circuit 104 is placed in the loop of the VCO 101, the upper limit of the acceptable data rate is defined by the sum of the total delay time of delay circuits constituting the VCO 101 and the delay time of the logic circuit 104. Therefore, this clock recovery circuit is not suitable for superfast data transmission.